Freescale Semiconductor /MK24F12 /MCG /C6

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Interpret as C6

PLLS=0, CME0=0, LOLIE0=0, VDIV0=0

Description

MCG Control 6 Register

Fields

VDIV0	VCO 0 Divider 0 (0): Multiply Factor is 24 1 (1): Multiply Factor is 25 2 (2): Multiply Factor is 26 3 (3): Multiply Factor is 27 4 (4): Multiply Factor is 28 5 (5): Multiply Factor is 29 6 (6): Multiply Factor is 30 7 (7): Multiply Factor is 31 8 (8): Multiply Factor is 32 9 (9): Multiply Factor is 33 10 (10): Multiply Factor is 34 11 (11): Multiply Factor is 35 12 (12): Multiply Factor is 36 13 (13): Multiply Factor is 37 14 (14): Multiply Factor is 38 15 (15): Multiply Factor is 39 16 (16): Multiply Factor is 40 17 (17): Multiply Factor is 41 18 (18): Multiply Factor is 42 19 (19): Multiply Factor is 43 20 (20): Multiply Factor is 44 21 (21): Multiply Factor is 45 22 (22): Multiply Factor is 46 23 (23): Multiply Factor is 47 24 (24): Multiply Factor is 48 25 (25): Multiply Factor is 49 26 (26): Multiply Factor is 50 27 (27): Multiply Factor is 51 28 (28): Multiply Factor is 52 29 (29): Multiply Factor is 53 30 (30): Multiply Factor is 54 31 (31): Multiply Factor is 55
CME0	Clock Monitor Enable 0 (0): External clock monitor is disabled for OSC0. 1 (1): External clock monitor is enabled for OSC0.
PLLS	PLL Select 0 (0): FLL is selected. 1 (1): PLL is selected (PRDIV 0 need to be programmed to the correct divider to generate a PLL reference clock in the range of 2-4 MHz prior to setting the PLLS bit).
LOLIE0	Loss of Lock Interrrupt Enable 0 (0): No interrupt request is generated on loss of lock. 1 (1): Generate an interrupt request on loss of lock.

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